Synopsys reported that Mellanox, NVIDIA’s networking business unit, will use its silicon-proven DesignWare DDR5/4 PHY IP to tackle emerging memory requirements InfiniBand networking chips, targeting high-performance computing and artificial intelligence (AI) applications. With up to 80-bit data path and support for multiple DIMMs per interface, the high-quality DesignWare DDR5/4 IP addresses critical data rate and memory capacity requirements.

NVIDIA is extending its efforts in high-performance and cloud computing. DesignWare DDR5/4 PHY IP is a part of Synopsys’ broad portfolio of IP memory interfaces consisting of controllers, PHYs, and IP verification for a wide range of processes. It supports all the required features that will help Mellanox integrate the IP into its less risky ASICs and SoCs.

To help consumers reduce their risk of adopting new protocols, Synopsys’ DesignWare DDR5/4 PHY IP provides firmware-based training, a field-upgradable one that does not require any changes to the hardware. Firmware-based programming also enables the use of intricate training patterns, allowing for the highest system-level margin and channel efficiency. For power performance, the DDR5/4 PHY IP of Synopsys provides many low power states with low output latencies and several pre-trained conditions for dynamic frequency change capability.

Logic libraries, embedded test, embedded memories, analog IP, wired and wireless interface IP, security IP, embedded processors, and subsystems are the various components of the DesignWare IP portfolio. To speed up software development and integration of IP into SoCs, Synopsys’ IP Accelerated initiative provides IP software development kits, IP prototyping kits, and IP subsystems; all these help to accelerate prototyping. The extensive investment made by Synopsys in IP quality, comprehensive technical support, and a robust IP development methodology enable designers to reduce the risk of integration and accelerate the time to market.

John Koeter, Senior Vice President of Marketing and Strategy for IP, Synopsys, said, “High-performance ASICs and SoCs for data-intensive networking and artificial intelligence applications require high-bandwidth off-chip memory technologies that efficiently minimize performance bottlenecks.”

He also added, “The DesignWare DDR5/4 PHY IP, operating at maximum data rates with differentiated features like firmware-based training, allows companies like NVIDIA to implement the latest functionality in their designs with less risk.”

“Our choice of Synopsys’ DesignWare IP for our latest InfiniBand solutions with in-network computing capabilities builds on our long history of integrating their high-quality IP into our silicon,” said Shlomit Weiss, Senior Vice President of Engineering at NVIDIA’s Mellanox business. “Synopsys’ DDR PHY IP is the best available solution to help us overcome stringent memory requirements while giving us the quality, capacity, and performance we need to deliver differentiated products,” he added.